1. Field of the Invention
The present invention relates to a non-volatile memory (NVM) cell structure, a NVM array structure and a method of fabricating a NVM cell structure, and more particularly, to an electrically erasable programmable (EEP) NVM cell structure and an EEP NVM array structure and a method of fabricating the EEP NVM cell structure.
2. Description of the Prior Art
Non-volatile memory (NVM) is a type of memory that retains information it stores even when no power is supplied to memory blocks thereof. Some examples include magnetic devices, optical discs, flash memory, and other semiconductor-based memory topologies.
For example, U.S. Pat. No. 6,678,190 discloses a single-poly NVM having two serially connected PMOS transistors wherein the control gate is omitted in the structure for layout as the bias is not necessary to apply to the floating gate during the programming mode. A first PMOS transistor acts as a select transistor. A second PMOS transistor is connected to the first PMOS transistor. A gate of the second PMOS transistor serves as a floating gate. The floating gate is selectively programmed or erased to store predetermined charges. However, the electrical erase fails to be utilized to remove the electric charges in the floating gate. That is, for achieving the data-erasing function, the electric charges stored in the floating gate should be removed from the floating gate by exposing ultraviolet (UV) light to the NVM. These NVMs are named as one time programming (OTP) memories. Accordingly, the need exists for multi-times programming (MTP) memories design.